RV32C RISC-Vマシン語表 （asm15r、抜粋）
| 代入 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| Rd = n6 | 0 | 1 | 0 | n5 | Rd | n4-0 | 0 | 1 | c.li |
| Rd = n18 | 0 | 1 | 1 | n17 | Rd | n16-12 | 0 | 1 | c.lui |
| Rd = Rm | 1 | 0 | 0 | 0 | Rd | Rm | 1 | 0 | c.mv |
※RdはR0以外、R0=0固定
※n18の下位12ビットは0固定
| 演算 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| Rd += n6 | 0 | 0 | 0 | n5 | Rd | n4-0 | 0 | 1 | c.addi |
| Rd <<= u5 | 0 | 0 | 0 | 0 | Rd | u4-0 | 1 | 0 | c.slli |
| Rd += Rm | 1 | 0 | 0 | 1 | Rd | Rm | 1 | 0 | c.add |
| Rd' >>= u5 | 1 | 0 | 0 | 0 | 0 | 0 | Rd' | u4-0 | 0 | 1 | c.srli |
| Rd' >>>= u5 | 1 | 0 | 0 | 0 | 0 | 1 | Rd' | u4-0 | 0 | 1 | c.srai |
| Rd' &= n6 | 1 | 0 | 0 | n5 | 1 | 0 | Rd' | n4-0 | 0 | 1 | c.andi |
| Rd' -= Rm' | 1 | 0 | 0 | 0 | 1 | 1 | Rd' | 0 | 0 | Rm' | 0 | 1 | c.sub |
| Rd' ^= Rm' | 1 | 0 | 0 | 0 | 1 | 1 | Rd' | 0 | 1 | Rm' | 0 | 1 | c.xor |
| Rd' |= Rm' | 1 | 0 | 0 | 0 | 1 | 1 | Rd' | 1 | 0 | Rm' | 0 | 1 | c.or |
| Rd' &= Rm' | 1 | 0 | 0 | 0 | 1 | 1 | Rd' | 1 | 1 | Rm' | 0 | 1 | c.and |
※Rd' = R(d+8) (3bitでR8-R15を指定)
※ >> : 符号なし右シフト、>>> : 符号付き右シフト
| M拡張演算 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| Rd = Rm * Rs | Rm0 | 0 | 0 | 0 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | mul |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | Rs | Rm4-1 | - |
| Rd = Rm / Rs | Rm0 | 1 | 0 | 0 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | div |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | Rs | Rm4-1 | - |
| Rd = Rm % Rs | Rm0 | 1 | 1 | 0 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | rem |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | Rs | Rm4-1 | - |
| Rd = MULH(Rm, Rs) | Rm0 | 0 | 0 | 1 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | mulh |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | Rs | Rm4-1 | - |
| Rd = MULHSU(Rm, Rs) | Rm0 | 0 | 1 | 0 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | mulhsu |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | Rs | Rm4-1 | - |
| Rd = MULHU(Rm, Rs) | Rm0 | 0 | 1 | 1 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | mulhu |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | Rs | Rm4-1 | - |
| Rd = DIVU(Rm, Rs) | Rm0 | 1 | 0 | 1 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | divu |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | Rs | Rm4-1 | - |
| Rd = REMU(Rm, Rs) | Rm0 | 1 | 1 | 1 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | remu |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | Rs | Rm4-1 | - |
※mul/div/remにC命令なし
※MULH:乗算結果の上位, MULHSU:符号付きRm×符号なしRsの上位, MULHU:符号なし乗算結果の上位
※DIVU:符号なし除算, REU:符号なし剰余
| メモリアクセス | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| Rd' = [Rn' + u7]L | 0 | 1 | 0 | u5-3 | Rn' | u2 | u6 | Rd' | 0 | 0 | c.lw |
| [Rn' + u7]L = Rd' | 1 | 1 | 0 | u5-3 | Rn' | u2 | u6 | Rd' | 0 | 0 | c.sw |
※[]後の記号でメモリサイズと符号を表す（W:2byte、L:4byte、C:符号付き1byte、S:符号付き2byte）
※u7:1byte単位のオフセット (4の倍数でなければならない)
| 分岐 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| IF !Rs' GOTO n9 | 1 | 1 | 0 | n8 | n4-3 | Rs' | n7-6 | n2-1 | n5 | 0 | 1 | c.beqz |
| IF Rs' GOTO n9 | 1 | 1 | 1 | n8 | n4-3 | Rs' | n7-6 | n2-1 | n5 | 0 | 1 | c.bnez |
| GOTO n12 | 1 | 0 | 1 | n11 | n4 | n9-8 | n10 | n6 | n7 | n3-1 | n5 | 0 | 1 | c.j |
| GOTO Rs | 1 | 0 | 0 | 0 | Rs | 0 | 0 | 0 | 0 | 0 | 1 | 0 | c.jr |
| GOSUB n12 | 0 | 0 | 1 | n11 | n4 | n9-8 | n10 | n6 | n7 | n3-1 | n5 | 0 | 1 | c.jal |
| GOSUB Rs | 1 | 0 | 0 | 1 | Rs | 0 | 0 | 0 | 0 | 0 | 1 | 0 | c.jalr |
| RET (=GOTO R1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | c.ret? |
※n9/n12:飛び先とのハーフワード(2byte)数の差分
| スタック | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| PUSH Rs,u8 | 1 | 1 | 0 | u5-2 | u7-6 | Rs | 1 | 0 | c.swsp |
| POP Rd,u8 | 0 | 1 | 0 | u5 | Rd | u4-2 | u7-6 | 1 | 0 | c.lwsp |
| Rd' = SP + u10 | 0 | 0 | 0 | u5-4 | u9-6 | u2 | u3 | Rd' | 0 | 0 | c.addi4spn |
| SP += n10 | 0 | 1 | 1 | n9 | 0 | 0 | 0 | 1 | 0 | n4 | n6 | n8-7 | n5 | 0 | 1 | c.addi16sp |
※PUSH: [SP + 4*u8]L = Rs, POP: Rd = [SP + 4*u8]L (スタックポインタは変化しない)
※u8/u10:4byte単位のオフセット
※SP+=n10: n10は16byte単位
※SP = R2
| その他 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| NOP (=1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | c.nop |
| BKPT | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | c.ebreak |
| WFI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | wfi |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | - |
※NOP:なにもしない(no operation) R0+=0
| 32bit代入 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| Rd = n32 | n15-12 | Rd | 0 | 1 | 1 | 0 | 1 | 1 | 1 | lui |
| n31-16 | - |
※n32の下位12ビットは0固定
| 32bit演算 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| Rd = PC + n32 | n15-12 | Rd | 0 | 0 | 1 | 0 | 1 | 1 | 1 | auipc |
| n31-16 | - |
| Rd = Rm + n12 | Rm0 | 0 | 0 | 0 | Rd | 0 | 0 | 1 | 0 | 0 | 1 | 1 | addi |
| n12 | Rm4-1 | - |
| Rd = Rm + Rs | Rm0 | 0 | 0 | 0 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | add |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rs | Rm4-1 | - |
| Rd = Rm - Rs | Rm0 | 0 | 0 | 0 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | sub |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | Rs | Rm4-1 | - |
| Rd = Rm << u5 | Rm0 | 0 | 0 | 1 | Rd | 0 | 0 | 1 | 0 | 0 | 1 | 1 | slli |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | u5 | Rm4-1 | - |
| Rd = Rm >> u5 | Rm0 | 1 | 0 | 1 | Rd | 0 | 0 | 1 | 0 | 0 | 1 | 1 | srli |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | u5 | Rm4-1 | - |
| Rd = Rm >>> u5 | Rm0 | 1 | 0 | 1 | Rd | 0 | 0 | 1 | 0 | 0 | 1 | 1 | srai |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | u5 | Rm4-1 | - |
| Rd = Rm << Rs | Rm0 | 0 | 0 | 1 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | sll |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rs | Rm4-1 | - |
| Rd = Rm >> Rs | Rm0 | 1 | 0 | 1 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | srl |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rs | Rm4-1 | - |
| Rd = Rm >>> Rs | Rm0 | 1 | 0 | 1 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | sra |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | Rs | Rm4-1 | - |
| Rd = Rm ^ n12 | Rm0 | 1 | 0 | 0 | Rd | 0 | 0 | 1 | 0 | 0 | 1 | 1 | xori |
| n12 | Rm4-1 | - |
| Rd = Rm | n12 | Rm0 | 1 | 1 | 0 | Rd | 0 | 0 | 1 | 0 | 0 | 1 | 1 | ori |
| n12 | Rm4-1 | - |
| Rd = Rm & n12 | Rm0 | 1 | 1 | 1 | Rd | 0 | 0 | 1 | 0 | 0 | 1 | 1 | andi |
| n12 | Rm4-1 | - |
| Rd = Rm ^ Rs | Rm0 | 1 | 0 | 0 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | xor |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rs | Rm4-1 | - |
| Rd = Rm | Rs | Rm0 | 1 | 1 | 0 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | or |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rs | Rm4-1 | - |
| Rd = Rm & Rs | Rm0 | 1 | 1 | 1 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | and |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rs | Rm4-1 | - |
※n32:4096byte単位
※ >> : 符号なし右シフト、>>> : 符号付き右シフト
| 32bitメモリアクセス | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| Rd = [Rm + n12] | Rm0 | 1 | 0 | 0 | Rd | 0 | 0 | 0 | 0 | 0 | 1 | 1 | lbu |
| n12 | Rm4-1 | - |
| Rd = [Rm + n12]C | Rm0 | 0 | 0 | 0 | Rd | 0 | 0 | 0 | 0 | 0 | 1 | 1 | lb |
| n12 | Rm4-1 | - |
| Rd = [Rm + n12]W | Rm0 | 1 | 0 | 1 | Rd | 0 | 0 | 0 | 0 | 0 | 1 | 1 | lhu |
| n12 | Rm4-1 | - |
| Rd = [Rm + n12]S | Rm0 | 0 | 0 | 1 | Rd | 0 | 0 | 0 | 0 | 0 | 1 | 1 | lh |
| n12 | Rm4-1 | - |
| Rd = [Rm + n12]L | Rm0 | 0 | 1 | 0 | Rd | 0 | 0 | 0 | 0 | 0 | 1 | 1 | lw |
| n12 | Rm4-1 | - |
| [Rm + n12] = Rs | Rm0 | 0 | 0 | 0 | n4-0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | sb |
| n11-5 | Rs | Rm4-1 | - |
| [Rm + n12]W = Rs | Rm0 | 0 | 0 | 1 | n4-0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | sh |
| n11-5 | Rs | Rm4-1 | - |
| [Rm + n12]L = Rs | Rm0 | 0 | 1 | 0 | n4-0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | sw |
| n11-5 | Rs | Rm4-1 | - |
※[]後の記号でメモリサイズと符号を表す（W:2byte、L:4byte、C:符号付き1byte、S:符号付き2byte）
※オフセットはサイズにかかわらず1byte単位
| 32bit比較 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| Rd = Rm < n12 | Rm0 | 0 | 1 | 0 | Rd | 0 | 0 | 1 | 0 | 0 | 1 | 1 | slti |
| n12 | Rm4-1 | - |
| Rd = LTU(Rm, n12) | Rm0 | 0 | 1 | 1 | Rd | 0 | 0 | 1 | 0 | 0 | 1 | 1 | sltiu |
| n12 | Rm4-1 | - |
| Rd = Rm < Rs | Rm0 | 0 | 1 | 0 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | slt |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rs | Rm4-1 | - |
| Rd = LTU(Rm, Rs) | Rm0 | 0 | 1 | 1 | Rd | 0 | 1 | 1 | 0 | 0 | 1 | 1 | sltu |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rs | Rm4-1 | - |
※Rmの方が小さければ1、そうでなければ0となる
※LTU:符号なし比較
| 32bit分岐 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| JAL Rd, n21 | n15-12 | Rd | 1 | 1 | 0 | 1 | 1 | 1 | 1 | jal |
| n20 | n10-1 | n11 | n19-16 | - |
| JALR Rd, Rs + n12 | Rs0 | 0 | 0 | 0 | Rd | 1 | 1 | 0 | 0 | 1 | 1 | 1 | jalr |
| n12 | Rs4-1 | - |
| IF Rm = Rs GOTO n13 | Rm0 | 0 | 0 | 0 | n4-1 | n11 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | beq |
| n12 | n10-5 | Rs | Rm4-1 | - |
| IF Rm != Rs GOTO n13 | Rm0 | 0 | 0 | 1 | n4-1 | n11 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | bne |
| n12 | n10-5 | Rs | Rm4-1 | - |
| IF Rm < Rs GOTO n13 | Rm0 | 1 | 0 | 0 | n4-1 | n11 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | blt |
| n12 | n10-5 | Rs | Rm4-1 | - |
| IF Rm >= Rs GOTO n13 | Rm0 | 1 | 0 | 1 | n4-1 | n11 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | bge |
| n12 | n10-5 | Rs | Rm4-1 | - |
| IF LTU(Rm, Rs) GOTO n13 | Rm0 | 1 | 1 | 0 | n4-1 | n11 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | bltu |
| n12 | n10-5 | Rs | Rm4-1 | - |
| IF GEU(Rm, Rs) GOTO n13 | Rm0 | 1 | 1 | 1 | n4-1 | n11 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | bgeu |
| n12 | n10-5 | Rs | Rm4-1 | - |
※n21,n13(IF系):飛び先とのハーフワード(2byte)数の差分
※n12(JALR):1byte単位
| 32bit CSR操作 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| CSRRW Rd, u12, Rs | Rs0 | 0 | 0 | 1 | Rd | 1 | 1 | 1 | 0 | 0 | 1 | 1 | csrrw |
| u12 | Rs4-1 | - |
| CSRRS Rd, u12, Rs | Rs0 | 0 | 1 | 0 | Rd | 1 | 1 | 1 | 0 | 0 | 1 | 1 | csrrs |
| u12 | Rs4-1 | - |
| CSRRC Rd, u12, Rs | Rs0 | 0 | 1 | 1 | Rd | 1 | 1 | 1 | 0 | 0 | 1 | 1 | csrrc |
| u12 | Rs4-1 | - |
| CSRRWI Rd, u12, u5 | u0 | 1 | 0 | 1 | Rd | 1 | 1 | 1 | 0 | 0 | 1 | 1 | csrrwi |
| u12 | u4-1 | - |
| CSRRSI Rd, u12, u5 | u0 | 1 | 1 | 0 | Rd | 1 | 1 | 1 | 0 | 0 | 1 | 1 | csrrsi |
| u12 | u4-1 | - |
| CSRRCI Rd, u12, u5 | u0 | 1 | 1 | 1 | Rd | 1 | 1 | 1 | 0 | 0 | 1 | 1 | csrrci |
| u12 | u4-1 | - |
| CPSID | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | csrrci |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | - |
| CPSIE | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | csrrsi |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | - |
※CPSID:割り込み禁止 CSRRCI R0, #300, 8
※CPSIE:割り込み許可 CSRRSI R0, #300, 8
| 32bitその他 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | op |
|---|
| FENCE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | fence |
| 0 | 0 | 0 | 0 | PI | PO | PR | PW | SI | SO | SR | SW | 0 | 0 | 0 | 0 | - |
| FENCE.TSO | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | fence.tso |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | - |
| ECALL | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | ecall |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | - |
| EBREAK | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | ebreak |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | - |
| MRET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | mret |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | - |
比べてみよう、RISC-VとArm、RISC-V対応かんたんマシン語「asm15r」
Cortex-M0 Armマシン語表(asm15)
DATA: Specifications - RISC-V Foundation
Original Text: CC BY ichigojam.net
Modified By みけCAT
Modification: CC BY 4.0 by みけCAT